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2514ps?avr?07/06 features ? high performance, low power avr ? 8-bit microcontroller ? advanced risc architecture ? 130 powerful instructions ? most single clock cycle execution ? 32 x 8 general purpose working registers ? fully static operation ? up to 16 mips throughput at 16 mhz ? on-chip 2-cycle multiplier ? non-volatile progra m and data memories ? 16k bytes of in-system self-programmable flash endurance: 10,000 write/erase cycles ? optional boot code section with independent lock bits in-system programming by on-chip boot program true read-while-w rite operation ? 512 bytes eeprom endurance: 100,000 write/erase cycles ? 1k byte internal sram ? programming lock for software security ? jtag (ieee std. 1149.1 compliant) interface ? boundary-scan capabilities a ccording to the jtag standard ? extensive on-chip debug support ? programming of flash, eeprom, fuses, an d lock bits through the jtag interface ? peripheral features ? 4 x 25 segment lcd driver ? two 8-bit timer/counters with se parate prescaler and compare mode ? one 16-bit timer/counter with separate prescaler, compare mode, and capture mode ? real time counter with separate oscillator ? four pwm channels ? 8-channel, 10-bit adc ? programmable serial usart ? master/slave spi serial interface ? universal serial interface wi th start condition detector ? programmable watchdog timer with separate on-chip oscillator ? on-chip analog comparator ? interrupt and wake-up on pin change ? special microcontroller features ? power-on reset and programmable brown-out detection ? internal calibrated oscillator ? external and internal interrupt sources ? five sleep modes: idle, adc noise re duction, power-save, power-down, and standby ? i/o and packages ? 53 programmable i/o lines ? 64-lead tqfp and 64-pad qfn/mlf ? speed grade: ? atmega169v: 0 - 4 mhz @ 1.8 - 5.5v, 0 - 8 mhz @ 2.7 - 5.5v ? atmega169: 0 - 8 mhz @ 2.7 - 5.5v, 0 - 16 mhz @ 4.5 - 5.5v ? temperature range: ? -40c to 85c industrial ? ultra-low power consumption ? active mode: 1 mhz, 1.8v: 350a 32 khz, 1.8v: 20a (including oscillator) 32 khz, 1.8v: 40a (inclu ding oscillator and lcd) ? power-down mode: 0.1a at 1.8v 8-bit microcontroller with 16k bytes in-system programmable flash atmega169v atmega169 summary notice: not recommended in new designs. note: this is a summary do cument. a complete document is available on our web site at www.atmel.com.
2 atmega169/v 2514ps?avr?07/06 pin configurations figure 1. pinout atmega169 note: the large center pad underneath the qfn/mlf packages is made of metal and internally connected to gnd. it should be soldered or glued to the board to ensure good mechani- cal stability. if the center pad is left uncon nected, the package might loosen from the board. disclaimer typical values contained in this datasheet are based on simulations and characteriza- tion of other avr microcontrollers manufactured on the same process technology. min and max values will be available afte r the device is characterized. pc0 (seg12) vcc gnd pf0 (adc0) pf7 (adc7/tdi) pf1 (adc1) pf2 (adc2) pf3 (adc3) pf4 (adc4/tck) pf5 (adc5/tms) pf6 (adc6/tdo) aref gnd avcc 17 61 60 18 59 20 58 19 21 57 22 56 23 55 24 54 25 53 26 52 27 51 29 28 50 49 32 31 30 (rxd/pcint0) pe0 (txd/pcint1) pe1 lcdcap (xck/ain0/pcint2) pe2 (ain1/pcint3) pe3 (usck/scl/pcint4) pe4 (di/sda/pcint5) pe5 (do/pcint6) pe6 (clko/pcint7) pe7 (ss/pcint8) pb0 (sck/pcint9) pb1 (mosi/pcint10) pb2 (miso/pcint11) pb3 (oc0a/pcint12) pb4 (oc2a/pcint15) pb7 (t1/seg24) pg3 (oc1b/pcint14) pb6 (t0/seg23) pg4 (oc1a/pcint13) pb5 pc1 (seg11) pg0 (seg14) (seg15) pd7 pc2 (seg10) pc3 (seg9) pc4 (seg8) pc5 (seg7) pc6 (seg6) pc7 (seg5) pa7 (seg3) pg2 (seg4) pa6 (seg2) pa5 (seg1) pa4 (seg0) pa3 (com3) pa0 (com0) pa1 (com1) pa2 (com2) pg1 (seg13) (seg16) pd6 (seg17) pd5 (seg18) pd4 (seg19) pd3 (seg20) pd2 (int0/seg21) pd1 (icp1/seg22) pd0 (tosc1) xtal1 (tosc2) xtal2 reset gnd vcc atmega169 index corner 2 3 1 4 5 6 7 8 9 10 11 12 13 14 16 15 64 63 62 47 46 48 45 44 43 42 41 40 39 38 37 36 35 33 34
3 atmega169/v 2514ps?avr?07/06 overview the atmega169 is a low-power cmos 8-bit microcontroller based on the avr enhanced risc architecture. by executing powerful instructions in a single clock cycle, the atm ega169 achieves throughputs approaching 1 mips per mhz allowing the system designer to optimize power consumption versus processing speed. block diagram figure 2. block diagram program counter internal oscillator watchdog timer stack pointer program flash mcu control register sram general purpose registers instruction register timer/ counters instruction decoder data dir. reg. portb data dir. reg. porte data dir. reg. porta data dir. reg. portd data register portb data register porte data register porta data register portd timing and control oscillator interrupt unit eeprom spi usart status register z y x alu portb drivers porte drivers porta drivers portf drivers portd drivers portc drivers pb0 - pb7 pe0 - pe7 pa0 - pa7 pf0 - pf7 vcc gnd aref xtal1 xtal2 control lines + - analog comp arator pc0 - pc7 8-bit data bus reset avcc calib. osc data dir. reg. portc data register portc on-chip debug jtag tap programming logic boundary- scan data dir. reg. portf data register portf adc pd0 - pd7 data dir. reg. portg data reg. portg portg drivers pg0 - pg4 universal serial interface avr cpu lcd controller/ driver
4 atmega169/v 2514ps?avr?07/06 the avr core combines a rich instruction se t with 32 general purpose working registers. all the 32 registers are directly connected to the arithmetic logic unit (alu), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. the resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional cisc microcontrollers. the atmega169 provides the following features: 16k bytes of in-system programmable flash with read-while-write capabilities , 512 bytes eeprom, 1k byte sram, 53 general purpose i/o lines, 32 general purpose working registers, a jtag interface for boundary-scan, on-chip debugging support and programming, a complete on-chip lcd controller with internal step-up voltage, three flexible timer/counters with compare modes, internal and external interrupts, a serial programmable usart, universal serial interface with start condition detector, an 8-channel, 10-bit adc, a programmable watchdog timer with internal os cillator, an spi serial port, and five software selectable power saving modes. the idle mode stops the cpu while allowing the sram, timer/counters, spi port, and interrupt system to continue functioning. the power- down mode saves the register contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset. in power-save mode, the asyn- chronous timer and the lcd controller continues to run, allowing the user to maintain a timer base and operate the lcd display while the rest of the device is sleeping. the adc noise reduction mode stops the cpu and all i/o modules except asynchronous timer, lcd controller and adc, to minimize switching noise during adc conversions. in standby mode, the crystal/res onator oscillator is running whil e the rest of the device is sleeping. this allows very fast start-up combined with low-power consumption. the device is manufactured using atmel?s high density non-volatile memory technology. the on-chip isp flash allows the program memory to be reprogrammed in-system through an spi serial interface, by a conventional non-volatile memory programmer, or by an on-chip boot program running on the avr core. the boot program can use any interface to download the application program in the application flash memory. soft- ware in the boot flas h section will continue to run while the application flash section is updated, providing true read-while-write operation. by combining an 8-bit risc cpu with in-system self-programmable flash on a monolithic chip, the atmel atmega169 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. the atmega169 avr is supported with a full suite of program and system development tools including: c compilers, macro assemblers, program debugger/simulators, in-cir- cuit emulators, and evaluation kits.
5 atmega169/v 2514ps?avr?07/06 pin descriptions vcc digital supply voltage. gnd ground. port a (pa7..pa0) port a is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port a output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port a pi ns that are externally pulled low will source current if the pull-up resistors are activated. the port a pins are tri-stated when a reset condition becomes active, even if the clock is not running. port a also serves the functions of various special features of the atmega169 as listed on page 62. port b (pb7..pb0) port b is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port b output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port b pi ns that are externally pulled low will source current if the pull-up resistors are activated. the port b pins are tri-stated when a reset condition becomes active, even if the clock is not running. port b has better driving ca pabilities than th e other ports. port b also serves the functions of various special features of the atmega169 as listed on page 63. port c (pc7..pc0) port c is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port c output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port c pi ns that are externally pulled low will source current if the pull-up resistors are activated. the port c pins are tri-stated when a reset condition becomes active, even if the clock is not running. port c also serves the functions of special features of the atmega169 as listed on page 66. port d (pd7..pd0) port d is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port d output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port d pi ns that are externally pulled low will source current if the pull-up resistors are activated. the port d pins are tri-stated when a reset condition becomes active, even if the clock is not running. port d also serves the functions of various special features of the atmega169 as listed on page 68. port e (pe7..pe0) port e is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port e output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port e pi ns that are externally pulled low will source current if the pull-up resistors are activated. the port e pins are tri-stated when a reset condition becomes active, even if the clock is not running. port e also serves the functions of various special features of the atmega169 as listed on page 70. port f (pf7..pf0) port f serves as the analog inputs to the a/d converter. port f also serves as an 8-bit bi-directional i/o port, if the a/d converter is not used. port pins can provide internal pull-up resistors (selected for each bit). the port f output
6 atmega169/v 2514ps?avr?07/06 buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port f pins that are externally pulled low will source current if the pull-up resistors are activated. the port f pins are tri-stated when a reset condition becomes active, even if the clock is not running. if th e jtag interface is enabled, the pull-up resis- tors on pins pf7(tdi), pf 5(tms), and pf4(tck) will be activated even if a reset occurs. port f also serves the functions of the jtag interface. port g (pg4..pg0) port g is a 5-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port g output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port g pins that are externally pulled low will source current if the pull-up resistors are activated. the port g pins are tri-stated when a reset condition becomes active, even if the clock is not running. port g also serves the functions of various special features of the atmega169 as listed on page 70. reset reset input. a low level on this pin for longer than the minimu m pulse length will gener- ate a reset, even if the clock is not running. the minimum pulse length is given in table 16 on page 38. shorter pulses are not guaranteed to generate a reset. xtal1 input to the inverting oscillato r amplifier and input to the in ternal clock operating circuit. xtal2 output from the invert ing oscillator amplifier. avcc avcc is the supply voltage pin for port f and the a/d converter. it should be externally connected to v cc , even if the adc is not used. if the adc is used, it should be con- nected to v cc through a low-pass filter. aref this is the analog reference pin for the a/d converter. lcdcap an external capacitor (typical > 470 nf) must be connected to the lcdcap pin as shown in figure 98. this capacitor acts as a reservoir for lcd power (v lcd ). a large capacitance reduces ripple on v lcd but increases the time until vlcd reaches its target value.
7 atmega169/v 2514ps?avr?07/06 register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page (0xff) reserved ? ? ? ? ? ? ? ? (0xfe) lcddr18 ? ? ? ? ? ? ? seg324 224 (0xfd) lcddr17 seg323 seg322 seg321 seg 320 seg319 seg318 seg317 seg316 224 (0xfc) lcddr16 seg315 seg314 seg313 seg 312 seg311 seg310 seg309 seg308 224 (0xfb) lcddr15 seg307 seg306 seg305 seg 304 seg303 seg302 seg301 seg300 224 (0xfa) reserved ? ? ? ? ? ? ? ? (0xf9) lcddr13 ? ? ? ? ? ? ? seg224 224 (0xf8) lcddr12 seg223 seg222 seg221 seg 220 seg219 seg218 seg217 seg216 224 (0xf7) lcddr11 seg215 seg214 seg213 seg 212 seg211 seg210 seg209 seg208 224 (0xf6) lcddr10 seg207 seg206 seg205 seg 204 seg203 seg202 seg201 seg200 224 (0xf5) reserved ? ? ? ? ? ? ? ? (0xf4) lcddr8 ? ? ? ? ? ? ? seg124 224 (0xf3) lcddr7 seg123 seg122 seg121 seg120 seg119 seg118 seg117 seg116 224 (0xf2) lcddr6 seg115 seg114 seg113 seg112 seg111 seg110 seg109 seg108 224 (0xf1) lcddr5 seg107 seg106 seg105 seg104 seg103 seg102 seg101 seg100 224 (0xf0) reserved ? ? ? ? ? ? ? ? (0xef) lcddr3 ? ? ? ? ? ? ? seg024 224 (0xee) lcddr2 seg023 seg022 seg021 seg020 seg019 seg018 seg017 seg016 224 (0xed) lcddr1 seg015 seg014 seg013 seg012 seg011 seg010 seg09 seg008 224 (0xec) lcddr0 seg007 seg006 seg005 seg004 seg003 seg002 seg001 seg000 224 (0xeb) reserved ? ? ? ? ? ? ? ? (0xea) reserved ? ? ? ? ? ? ? ? (0xe9) reserved ? ? ? ? ? ? ? ? (0xe8) reserved ? ? ? ? ? ? ? ? (0xe7) lcdccr lcdcd2 lcdcd1 lcdcc0 ? lcdcc3 lcdcc2 lcdcc1 lcdcc0 222 (0xe6) lcdfrr ? lcdps2 lcdps1 lcdps0 ? lcdcd2 lcdcd1 lcdcd0 220 (0xe5) lcdcrb lcdcs lcd2b lcdmux1 lcdmux0 ? lcdpm2 lcdpm1 lcdpm0 219 (0xe4) lcdcra lcden lcdab ? lcdif lcdie ? ? lcdbl 218 (0xe3) reserved ? ? ? ? ? ? ? ? (0xe2) reserved ? ? ? ? ? ? ? ? (0xe1) reserved ? ? ? ? ? ? ? ? (0xe0) reserved ? ? ? ? ? ? ? ? (0xdf) reserved ? ? ? ? ? ? ? ? (0xde) reserved ? ? ? ? ? ? ? ? (0xdd) reserved ? ? ? ? ? ? ? ? (0xdc) reserved ? ? ? ? ? ? ? ? (0xdb) reserved ? ? ? ? ? ? ? ? (0xda) reserved ? ? ? ? ? ? ? ? (0xd9) reserved ? ? ? ? ? ? ? ? (0xd8) reserved ? ? ? ? ? ? ? ? (0xd7) reserved ? ? ? ? ? ? ? ? (0xd6) reserved ? ? ? ? ? ? ? ? (0xd5) reserved ? ? ? ? ? ? ? ? (0xd4) reserved ? ? ? ? ? ? ? ? (0xd3) reserved ? ? ? ? ? ? ? ? (0xd2) reserved ? ? ? ? ? ? ? ? (0xd1) reserved ? ? ? ? ? ? ? ? (0xd0) reserved ? ? ? ? ? ? ? ? (0xcf) reserved ? ? ? ? ? ? ? ? (0xce) reserved ? ? ? ? ? ? ? ? (0xcd) reserved ? ? ? ? ? ? ? ? (0xcc) reserved ? ? ? ? ? ? ? ? (0xcb) reserved ? ? ? ? ? ? ? ? (0xca) reserved ? ? ? ? ? ? ? ? (0xc9) reserved ? ? ? ? ? ? ? ? (0xc8) reserved ? ? ? ? ? ? ? ? (0xc7) reserved ? ? ? ? ? ? ? ? (0xc6) udr usart i/o data register 169 (0xc5) ubrrh usart baud rate register high 173 (0xc4) ubrrl usart baud rate register low 173 (0xc3) reserved ? ? ? ? ? ? ? ? (0xc2) ucsrc ? umsel upm1 upm0 usbs ucsz1 ucsz0 ucpol 169 (0xc1) ucsrb rxcie txcie udri e rxen txen ucsz2 rxb8 txb8 169 (0xc0) ucsra rxc txc udre fe dor upe u2x mpcm 169
8 atmega169/v 2514ps?avr?07/06 (0xbf) reserved ? ? ? ? ? ? ? ? (0xbe) reserved ? ? ? ? ? ? ? ? (0xbd) reserved ? ? ? ? ? ? ? ? (0xbc) reserved ? ? ? ? ? ? ? ? (0xbb) reserved ? ? ? ? ? ? ? ? (0xba) usidr usi data register 184 (0xb9) usisr usisif usioif usipf usid c usicnt3 usicnt2 usicnt1 usicnt0 185 (0xb8) usicr usisie usioie usiwm1 usiwm0 usics1 usics0 usiclk usitc 186 (0xb7) reserved ? ? ? ? ? ? ? (0xb6) assr ? ? ? exclk as2 tcn2ub ocr2ub tcr2ub 138 (0xb5) reserved ? ? ? ? ? ? ? ? (0xb4) reserved ? ? ? ? ? ? ? ? (0xb3) ocr2a timer/counter2 output compare register a 137 (0xb2) tcnt2 timer/counter2 (8-bit) 137 (0xb1) reserved ? ? ? ? ? ? ? ? (0xb0) tccr2a foc2a wgm20 com2a1 com2a0 wgm21 cs22 cs21 cs20 135 (0xaf) reserved ? ? ? ? ? ? ? ? (0xae) reserved ? ? ? ? ? ? ? ? (0xad) reserved ? ? ? ? ? ? ? ? (0xac) reserved ? ? ? ? ? ? ? ? (0xab) reserved ? ? ? ? ? ? ? ? (0xaa) reserved ? ? ? ? ? ? ? ? (0xa9) reserved ? ? ? ? ? ? ? ? (0xa8) reserved ? ? ? ? ? ? ? ? (0xa7) reserved ? ? ? ? ? ? ? ? (0xa6) reserved ? ? ? ? ? ? ? ? (0xa5) reserved ? ? ? ? ? ? ? ? (0xa4) reserved ? ? ? ? ? ? ? ? (0xa3) reserved ? ? ? ? ? ? ? ? (0xa2) reserved ? ? ? ? ? ? ? ? (0xa1) reserved ? ? ? ? ? ? ? ? (0xa0) reserved ? ? ? ? ? ? ? ? (0x9f) reserved ? ? ? ? ? ? ? ? (0x9e) reserved ? ? ? ? ? ? ? ? (0x9d) reserved ? ? ? ? ? ? ? ? (0x9c) reserved ? ? ? ? ? ? ? ? (0x9b) reserved ? ? ? ? ? ? ? ? (0x9a) reserved ? ? ? ? ? ? ? ? (0x99) reserved ? ? ? ? ? ? ? ? (0x98) reserved ? ? ? ? ? ? ? ? (0x97) reserved ? ? ? ? ? ? ? ? (0x96) reserved ? ? ? ? ? ? ? ? (0x95) reserved ? ? ? ? ? ? ? ? (0x94) reserved ? ? ? ? ? ? ? ? (0x93) reserved ? ? ? ? ? ? ? ? (0x92) reserved ? ? ? ? ? ? ? ? (0x91) reserved ? ? ? ? ? ? ? ? (0x90) reserved ? ? ? ? ? ? ? ? (0x8f) reserved ? ? ? ? ? ? ? ? (0x8e) reserved ? ? ? ? ? ? ? ? (0x8d) reserved ? ? ? ? ? ? ? ? (0x8c) reserved ? ? ? ? ? ? ? ? (0x8b) ocr1bh timer/counter1 - output compare register b high byte 121 (0x8a) ocr1bl timer/counter1 - output compare register b low byte 121 (0x89) ocr1ah timer/counter1 - output compare register a high byte 121 (0x88) ocr1al timer/counter1 - output compare register a low byte 121 (0x87) icr1h timer/counter1 - input capture register high byte 122 (0x86) icr1l timer/counter1 - input capture register low byte 122 (0x85) tcnt1h timer/counter1 - counter register high byte 121 (0x84) tcnt1l timer/counter1 - counter register low byte 121 (0x83) reserved ? ? ? ? ? ? ? ? (0x82) tccr1c foc1a foc1b ? ? ? ? ? ? 120 (0x81) tccr1b icnc1 ices1 ? wgm13 wgm12 cs12 cs11 cs10 119 (0x80) tccr1a com1a1 com1a0 com1b1 com1b0 ? ? wgm11 wgm10 117 (0x7f) didr1 ? ? ? ? ? ? ain1d ain0d 191 (0x7e) didr0 adc7d adc6d adc5d adc4d adc3d adc2d adc1d adc0d 208 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page
9 atmega169/v 2514ps?avr?07/06 (0x7d) reserved ? ? ? ? ? ? ? ? (0x7c) admux refs1 refs0 adlar mux4 mux3 mux2 mux1 mux0 204 (0x7b) adcsrb ?acme ? ? ? adts2 adts1 adts0 189, 208 (0x7a) adcsra aden adsc adate adif adie adps2 adps1 adps0 206 (0x79) adch adc data register high byte 207 (0x78) adcl adc data register low byte 207 (0x77) reserved ? ? ? ? ? ? ? ? (0x76) reserved ? ? ? ? ? ? ? ? (0x75) reserved ? ? ? ? ? ? ? ? (0x74) reserved ? ? ? ? ? ? ? ? (0x73) reserved ? ? ? ? ? ? ? ? (0x72) reserved ? ? ? ? ? ? ? ? (0x71) reserved ? ? ? ? ? ? ? ? (0x70) timsk2 ? ? ? ? ? ? ocie2a toie2 140 (0x6f) timsk1 ? ?icie1 ? ? ocie1b ocie1a toie1 122 (0x6e) timsk0 ? ? ? ? ? ? ocie0a toie0 92 (0x6d) reserved ? ? ? ? ? ? ? ? (0x6c) pcmsk1 pcint15 pcint14 pcint13 p cint12 pcint11 pcint10 pcint9 pcint8 54 (0x6b) pcmsk0 pcint7 pcint6 pcint5 pc int4 pcint3 pcint2 pcint1 pcint0 54 (0x6a) reserved ? ? ? ? ? ? ? ? (0x69) eicra ? ? ? ? ? ?isc01isc00 52 (0x68) reserved ? ? ? ? ? ? ? ? (0x67) reserved ? ? ? ? ? ? ? ? (0x66) osccal oscillator calibration register 28 (0x65) reserved ? ? ? ? ? ? ? ? (0x64) prr ? ? ? prlcd prtim1 prspi prusart0 pradc 34 (0x63) reserved ? ? ? ? ? ? ? ? (0x62) reserved ? ? ? ? ? ? ? ? (0x61) clkpr clkpce ? ? ? clkps3 clkps2 clkps1 clkps0 30 (0x60) wdtcr ? ? ? wdce wde wdp2 wdp1 wdp0 43 0x3f (0x5f) sreg i t h s v n z c 9 0x3e (0x5e) sph ? ? ? ? ? sp10 sp9 sp8 11 0x3d (0x5d) spl sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 11 0x3c (0x5c) reserved 0x3b (0x5b) reserved 0x3a (0x5a) reserved 0x39 (0x59) reserved 0x38 (0x58) reserved 0x37 (0x57) spmcsr spmie rwwsb ? rwwsre blbset pgwrt pgers spmen 256 0x36 (0x56) reserved ? ? ? ? ? ? ? ? 0x35 (0x55) mcucr jtd ? ?pud ? ? ivsel ivce 234 0x34 (0x54) mcusr ? ? ? jtrf wdrf borf extrf porf 235 0x33 (0x53) smcr ? ? ? ?sm2sm1sm0se 32 0x32 (0x52) reserved ? ? ? ? ? ? ? ? 0x31 (0x51) ocdr idrd/ocd ocdr6 ocdr5 ocdr4 ocdr3 ocdr2 ocdr1 ocdr0 230 0x30 (0x50) acsr acd acbg aco aci acie acic acis1 acis0 189 0x2f (0x4f) reserved ? ? ? ? ? ? ? ? 0x2e (0x4e) spdr spi data register 149 0x2d (0x4d) spsr spif wcol ? ? ? ? ? spi2x 149 0x2c (0x4c) spcr spie spe dord mstr cpol cpha spr1 spr0 147 0x2b (0x4b) gpior2 general purpose i/o register 2 22 0x2a (0x4a) gpior1 general purpose i/o register 1 22 0x29 (0x49) reserved ? ? ? ? ? ? ? ? 0x28 (0x48) reserved ? ? ? ? ? ? ? ? 0x27 (0x47) ocr0a timer/counter0 output compare register a 92 0x26 (0x46) tcnt0 timer/counter0 (8 bit) 91 0x25 (0x45) reserved ? ? ? ? ? ? ? ? 0x24 (0x44) tccr0a foc0a wgm00 com0a1 com0a0 wgm01 cs02 cs01 cs00 89 0x23 (0x43) gtccr tsm ? ? ? ? ? psr2 psr10 94 0x22 (0x42) eearh ? ? ? ? ? ? ?eear8 18 0x21 (0x41) eearl eeprom address register low byte 18 0x20 (0x40) eedr eeprom data register 18 0x1f (0x3f) eecr ? ? ? ? eerie eemwe eewe eere 18 0x1e (0x3e) gpior0 general purpose i/o register 0 22 0x1d (0x3d) eimsk pcie1 pcie0 ? ? ? ? ?int0 53 0x1c (0x3c) eifr pcif1 pcif0 ? ? ? ? ? intf0 53 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page
10 atmega169/v 2514ps?avr?07/06 note: 1. for compatibility with future devices, reserved bits shoul d be written to zero if accessed. reserved i/o memory addresse s should never be written. 2. i/o registers within the address range 0x00 - 0x1f are direct ly bit-accessible using the sbi and cbi instructions. in these registers, the value of single bits can be ch ecked by using the sbis and sbic instructions. 3. some of the status flags are cleared by writing a logical one to them. note that, unlike most other avrs, the cbi and sbi instructions will only operate on the specified bit, and can ther efore be used on registers containing such status flags. the cbi and sbi instructions work wit h registers 0x00 to 0x1f only. 4. when using the i/o specific commands in and out, the i/o addresses 0x00 - 0x3f must be used. when addressing i/o registers as data space using ld and st instructions, 0x 20 must be added to these addresses. the atmega169 is a com- plex microcontroller with more peripheral units than can be supported within the 64 location reserved in opcode for the in and out instructions. for the extended i/o space from 0x 60 - 0xff in sram, only the st/sts/std and ld/lds/ldd instructions can be used. 0x1b (0x3b) reserved ? ? ? ? ? ? ? ? 0x1a (0x3a) reserved ? ? ? ? ? ? ? ? 0x19 (0x39) reserved ? ? ? ? ? ? ? ? 0x18 (0x38) reserved ? ? ? ? ? ? ? ? 0x17 (0x37) tifr2 ? ? ? ? ? ? ocf2a tov2 141 0x16 (0x36) tifr1 ? ?icf1 ? ? ocf1b ocf1a tov1 123 0x15 (0x35) tifr0 ? ? ? ? ? ? ocf0a tov0 92 0x14 (0x34) portg ? ? ? portg4 portg3 portg2 portg1 portg0 78 0x13 (0x33) ddrg ? ? ? ddg4 ddg3 ddg2 ddg1 ddg0 78 0x12 (0x32) ping ? ? ? ping4 ping3 ping2 ping1 ping0 78 0x11 (0x31) portf portf7 portf6 portf5 portf4 portf3 portf2 portf1 portf0 77 0x10 (0x30) ddrf ddf7 ddf6 ddf5 ddf4 ddf3 ddf2 ddf1 ddf0 77 0x0f (0x2f) pinf pinf7 pinf6 pinf5 pinf4 pinf3 pinf2 pinf1 pinf0 78 0x0e (0x2e) porte porte7 porte6 porte5 porte4 porte3 porte2 porte1 porte0 77 0x0d (0x2d) ddre dde7 dde6 dde 5 dde4 dde3 dde2 dde1 dde0 77 0x0c (0x2c) pine pine7 pine6 pine5 pine4 pine3 pine2 pine1 pine0 77 0x0b (0x2b) portd portd7 portd6 portd 5 portd4 portd3 portd2 portd1 portd0 77 0x0a (0x2a) ddrd ddd7 ddd6 ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 77 0x09 (0x29) pind pind7 pind6 pind 5 pind4 pind3 pind2 pind1 pind0 77 0x08 (0x28) portc portc7 portc6 portc 5 portc4 portc3 portc2 portc1 portc0 76 0x07 (0x27) ddrc ddc7 ddc6 ddc5 ddc4 ddc3 ddc2 ddc1 ddc0 76 0x06 (0x26) pinc pinc7 pinc6 pinc 5 pinc4 pinc3 pinc2 pinc1 pinc0 77 0x05 (0x25) portb portb7 portb6 portb 5 portb4 portb3 portb2 portb1 portb0 76 0x04 (0x24) ddrb ddb7 ddb6 ddb 5 ddb4 ddb3 ddb2 ddb1 ddb0 76 0x03 (0x23) pinb pinb7 pinb6 pinb5 pinb4 pinb3 pinb2 pinb1 pinb0 76 0x02 (0x22) porta porta7 porta6 porta 5 porta4 porta3 porta2 porta1 porta0 76 0x01 (0x21) ddra dda7 dda6 dda 5 dda4 dda3 dda2 dda1 dda0 76 0x00 (0x20) pina pina7 pina6 pina5 pina4 pina3 pina2 pina1 pina0 76 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page
11 atmega169/v 2514ps?avr?07/06 instruction set summary mnemonics operands description operation flags #clocks arithmetic and logic instructions add rd, rr add two registers rd rd + rr z,c,n,v,h 1 adc rd, rr add with carry two registers rd rd + rr + c z,c,n,v,h 1 adiw rdl,k add immediate to word rdh:rdl rdh:rdl + k z,c,n,v,s 2 sub rd, rr subtract two registers rd rd - rr z,c,n,v,h 1 subi rd, k subtract constant from register rd rd - k z,c,n,v,h 1 sbc rd, rr subtract with carry two registers rd rd - rr - c z,c,n,v,h 1 sbci rd, k subtract with carry constant from reg. rd rd - k - c z,c,n,v,h 1 sbiw rdl,k subtract immediate from word rdh:rdl rdh:rdl - k z,c,n,v,s 2 and rd, rr logical and registers rd rd ? rr z,n,v 1 andi rd, k logical and register and constant rd rd ? k z,n,v 1 or rd, rr logical or registers rd rd v rr z,n,v 1 ori rd, k logical or register and constant rd rd v k z,n,v 1 eor rd, rr exclusive or registers rd rd rr z,n,v 1 com rd one?s complement rd 0xff ? rd z,c,n,v 1 neg rd two?s complement rd 0x00 ? rd z,c,n,v,h 1 sbr rd,k set bit(s) in register rd rd v k z,n,v 1 cbr rd,k clear bit(s) in register rd rd ? (0xff - k) z,n,v 1 inc rd increment rd rd + 1 z,n,v 1 dec rd decrement rd rd ? 1 z,n,v 1 tst rd test for zero or minus rd rd ? rd z,n,v 1 clr rd clear register rd rd rd z,n,v 1 ser rd set register rd 0xff none 1 mul rd, rr multiply unsigned r1:r0 rd x rr z,c 2 muls rd, rr multiply signed r1:r0 rd x rr z,c 2 mulsu rd, rr multiply signed with unsigned r1:r0 rd x rr z,c 2 fmul rd, rr fractional multiply unsigned r1:r0 (rd x rr) << 1 z,c 2 fmuls rd, rr fractional multiply signed r1:r0 (rd x rr) << 1 z,c 2 fmulsu rd, rr fractional multiply signed with unsigned r1:r0 (rd x rr) << 1 z,c 2 branch instructions rjmp k relative jump pc pc + k + 1 none 2 ijmp indirect jump to (z) pc z none 2 jmp k direct jump pc knone3 rcall k relative subroutine call pc pc + k + 1 none 3 icall indirect call to (z) pc znone3 call k direct subroutine call pc knone4 ret subroutine return pc stack none 4 reti interrupt return pc stack i 4 cpse rd,rr compare, skip if equal if (rd = rr) pc pc + 2 or 3 none 1/2/3 cp rd,rr compare rd ? rr z, n,v,c,h 1 cpc rd,rr compare with carry rd ? rr ? c z, n,v,c,h 1 cpi rd,k compare register with immediate rd ? k z, n,v,c,h 1 sbrc rr, b skip if bit in register cleared if (rr(b)=0) pc pc + 2 or 3 none 1/2/3 sbrs rr, b skip if bit in register is set if (rr(b)=1) pc pc + 2 or 3 none 1/2/3 sbic p, b skip if bit in i/o register cleared if (p(b)=0) pc pc + 2 or 3 none 1/2/3 sbis p, b skip if bit in i/o register is set if (p(b)=1) pc pc + 2 or 3 none 1/2/3 brbs s, k branch if status flag set if (sreg(s) = 1) then pc pc+k + 1 none 1/2 brbc s, k branch if status flag cleared if (sreg(s) = 0) then pc pc+k + 1 none 1/2 breq k branch if equal if (z = 1) then pc pc + k + 1 none 1/2 brne k branch if not equal if (z = 0) then pc pc + k + 1 none 1/2 brcs k branch if carry set if (c = 1) then pc pc + k + 1 none 1/2 brcc k branch if carry cleared if (c = 0) then pc pc + k + 1 none 1/2 brsh k branch if same or higher if (c = 0) then pc pc + k + 1 none 1/2 brlo k branch if lower if (c = 1) then pc pc + k + 1 none 1/2 brmi k branch if minus if (n = 1) then pc pc + k + 1 none 1/2 brpl k branch if plus if (n = 0) then pc pc + k + 1 none 1/2 brge k branch if greater or equal, signed if (n v= 0) then pc pc + k + 1 none 1/2 brlt k branch if less than zero, signed if (n v= 1) then pc pc + k + 1 none 1/2 brhs k branch if half carry flag set if (h = 1) then pc pc + k + 1 none 1/2 brhc k branch if half carry flag cleared if (h = 0) then pc pc + k + 1 none 1/2 brts k branch if t flag set if (t = 1) then pc pc + k + 1 none 1/2 brtc k branch if t flag cleared if (t = 0) then pc pc + k + 1 none 1/2 brvs k branch if overflow flag is set if (v = 1) then pc pc + k + 1 none 1/2 brvc k branch if overflow flag is cleared if (v = 0) then pc pc + k + 1 none 1/2
12 atmega169/v 2514ps?avr?07/06 brie k branch if interrupt enabled if ( i = 1) then pc pc + k + 1 none 1/2 brid k branch if interrupt disabled if ( i = 0) then pc pc + k + 1 none 1/2 bit and bit-test instructions sbi p,b set bit in i/o register i/o(p,b) 1none2 cbi p,b clear bit in i/o register i/o(p,b) 0none2 lsl rd logical shift left rd(n+1) rd(n), rd(0) 0 z,c,n,v 1 lsr rd logical shift right rd(n) rd(n+1), rd(7) 0 z,c,n,v 1 rol rd rotate left through carry rd(0) c,rd(n+1) rd(n),c rd(7) z,c,n,v 1 ror rd rotate right through carry rd(7) c,rd(n) rd(n+1),c rd(0) z,c,n,v 1 asr rd arithmetic shift right rd(n) rd(n+1), n=0..6 z,c,n,v 1 swap rd swap nibbles rd(3..0) rd(7..4),rd(7..4) rd(3..0) none 1 bset s flag set sreg(s) 1 sreg(s) 1 bclr s flag clear sreg(s) 0 sreg(s) 1 bst rr, b bit store from register to t t rr(b) t 1 bld rd, b bit load from t to register rd(b) tnone1 sec set carry c 1c1 clc clear carry c 0 c 1 sen set negative flag n 1n1 cln clear negative flag n 0 n 1 sez set zero flag z 1z1 clz clear ze ro flag z 0 z 1 sei global interrupt enable i 1i1 cli global interrupt disable i 0 i 1 ses set signed test flag s 1s1 cls clear signed test flag s 0 s 1 sev set twos complement overflow. v 1v1 clv clear twos complement overflow v 0 v 1 set set t in sreg t 1t1 clt clear t in sreg t 0 t 1 seh set half carry flag in sreg h 1h1 clh clear half carry flag in sreg h 0 h 1 data transfer instructions mov rd, rr move between registers rd rr none 1 movw rd, rr copy register word rd+1:rd rr+1:rr none 1 ldi rd, k load immediate rd knone1 ld rd, x load indirect rd (x) none 2 ld rd, x+ load indirect and post-inc. rd (x), x x + 1 none 2 ld rd, - x load indirect and pre-dec. x x - 1, rd (x) none 2 ld rd, y load indirect rd (y) none 2 ld rd, y+ load indirect and post-inc. rd (y), y y + 1 none 2 ld rd, - y load indirect and pre-dec. y y - 1, rd (y) none 2 ldd rd,y+q load indirect with displacement rd (y + q) none 2 ld rd, z load indirect rd (z) none 2 ld rd, z+ load indirect and post-inc. rd (z), z z+1 none 2 ld rd, -z load indirect and pre-dec. z z - 1, rd (z) none 2 ldd rd, z+q load indirect with displacement rd (z + q) none 2 lds rd, k load direct from sram rd (k) none 2 st x, rr store indirect (x) rr none 2 st x+, rr store indirect and post-inc. (x) rr, x x + 1 none 2 st - x, rr store indirect and pre-dec. x x - 1, (x) rr none 2 st y, rr store indirect (y) rr none 2 st y+, rr store indirect and post-inc. (y) rr, y y + 1 none 2 st - y, rr store indirect and pre-dec. y y - 1, (y) rr none 2 std y+q,rr store indirect with displacement (y + q) rr none 2 st z, rr store indirect (z) rr none 2 st z+, rr store indirect and post-inc. (z) rr, z z + 1 none 2 st -z, rr store indirect and pre-dec. z z - 1, (z) rr none 2 std z+q,rr store indirect with displacement (z + q) rr none 2 sts k, rr store direct to sram (k) rr none 2 lpm load program memory r0 (z) none 3 lpm rd, z load program memory rd (z) none 3 lpm rd, z+ load program memory and post-inc rd (z), z z+1 none 3 spm store program memory (z) r1:r0 none - in rd, p in port rd pnone1 out p, rr out port p rr none 1 push rr push register on stack stack rr none 2 mnemonics operands description operation flags #clocks
13 atmega169/v 2514ps?avr?07/06 pop rd pop register from stack rd stack none 2 mcu control instructions nop no operation none 1 sleep sleep (see specific descr. for sleep function) none 1 wdr watchdog reset (see specific descr. for wdr/timer) none 1 break break for on-chip debug only none n/a mnemonics operands description operation flags #clocks
14 atmega169/v 2514ps?avr?07/06 ordering information notes: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering info rmation and minimum quantities. 2. pb-free packaging alternative, complies to the european dire ctive for restriction of hazardous substances (rohs direc- tive). also halide free and fully green. 3. for speed vs. v cc , see figure 136 on page 300 and figure 137 on page 300. speed (mhz) (3) power supply ordering code package (1) operation range 8 1.8 - 5.5v atmega169v-8ai atmega169v-8au (2) atmega169v-8mi atmega169v-8mu (2) 64a 64a 64m1 64m1 industrial (-4 0 c to 85 c) 16 2.7 - 5.5v atmega169-16ai atmega169-16au (2) ATMEGA169-16MI atmega169-16mu (2) 64a 64a 64m1 64m1 industrial (-4 0 c to 85 c) package type 64a 64-lead, thin (1.0 mm) plastic gull wing quad flat package (tqfp) 64m1 64-pad, 9 x 9 x 1.0 mm body, lead pitch 0.50 mm, quad flat no-lead/micro lead frame package (qfn/ mlf)
15 atmega169/v 2514ps?avr?07/06 packaging information 64a 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 64a, 64-lead, 14 x 14 mm body size, 1.0 mm body thickness, 0.8 mm lead pitch, thin profile plastic quad flat package (tqfp) b 64a 10/5/2001 pin 1 identifier 0?~7? pin 1 l c a1 a2 a d1 d e e1 e b common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this package conforms to jedec reference ms-026, variation aeb. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. dimensions d1 and e1 are maximum plastic body size dimensions including mold mismatch. 3. lead coplanarity is 0.10 mm maximum. a ? ? 1.20 a1 0.05 ? 0.15 a2 0.95 1.00 1.05 d 15.75 16.00 16.25 d1 13.90 14.00 14.10 note 2 e 15.75 16.00 16.25 e1 13.90 14.00 14.10 note 2 b 0.30 ? 0.45 c 0.09 ? 0.20 l 0.45 ? 0.75 e 0.80 typ
16 atmega169/v 2514ps?avr?07/06 64m1 2 3 25 orch a rd p a rkw a y sa n jose, ca 951 3 1 title drawing no. r rev. 64m1 , 64-p a d, 9 x 9 x 1.0 mm body, le a d pitch 0.50 mm, g 64m1 5/25/06 common dimen s ion s (unit of me a sure = mm) s ymbol min nom max note a 0. 8 0 0.90 1.00 a1 ? 0.02 0.05 b 0.1 8 0.25 0. 3 0 d d2 5.20 5.40 5.60 8 .90 9.00 9.10 8 .90 9.00 9.10 e e2 5.20 5.40 5.60 e 0.50 b s c l0. 3 5 0.40 0.45 note: 1. jedec s t a nd a rd mo-220, ( s aw s ingul a tion) fig. 1, vmmd. 2. dimension a nd toler a nce conform to a s mey14.5m-1994. top view s ide view bottom view d e m a rked pin# 1 id s eating plane a1 c a c 0.0 8 1 2 3 k 1.25 1.40 1.55 e2 d2 b e pin #1 corner l pin #1 tr i a ngle pin #1 ch a mfer (c 0. 3 0) option a option b pin #1 notch (0.20 r) option c k k 5.40 mm exposed p a d, micro le a d fr a me p a ck a ge (mlf)
17 atmega169/v 2514ps?avr?07/06 errata atmega169 rev e ? interrupts may be lost when writing the timer registers in the asynchronous timer 1. interrupts may be lost when writing the timer registers in the asynchronous timer if one of the timer registers which is synchronized to the asynchronous timer2 clock is written in the cycle before a overflow interrupt occurs, the interrupt may be lost. problem fix/workaround always check that the timer2 timer/c ounter register, tcnt2, does not have the value 0xff before writing th e timer2 control register, tccr2, or output compare register, ocr2. atmega169 rev d ? interrupts may be lost when writing the timer registers in the asynchronous timer ? high serial resistance in the glass can result in dim segments on the lcd ? idcode masks data from tdi input 3. interrupts may be lost when writing the timer registers in the asynchronous timer if one of the timer registers which is synchronized to the asynchronous timer2 clock is written in the cycle before a overflow interrupt occurs, the interrupt may be lost. problem fix/workaround always check that the timer2 timer/c ounter register, tcnt2, does not have the value 0xff before writing th e timer2 control register, tccr2, or output compare register, ocr2. 2. high serial resistance in the glass can result in dim segments on the lcd some display types with high serial resistance (>20 k ) inside the glass can result in dim segments on the lcd problem fix/workaround add a 1 nf (0.47 - 1.5 nf) capacitor between each common pin and ground. 1. idcode masks data from tdi input the jtag instruction idcode is not workin g correctly. data to succeeding devices are replaced by all-ones during update-dr. problem fix / workaround ? if atmega169 is the only device in the scan chain, the problem is not visible. ? select the device id register of the atmega169 by issuing the idcode instruction or by entering the test-logic-reset state of the tap controller to read out the contents of its device id register and possibly data from succeeding devices of the scan chain. issue the bypass instruction to the atmega169 while reading the device id registers of preceding devices of the boundary scan chain. ? if the device ids of all devices in the boundary scan chain must be captured simultaneously, the atmega169 must be the first device in the chain.
18 atmega169/v 2514ps?avr?07/06 atmega169 rev c ? interrupts may be lost when writing the timer registers in the asynchronous timer ? high current consumption in power down when jtagen is programmed ? lcd contrast control ? some data combinations can result in dim segments on the lcd ? lcd current consumption ? idcode masks data from tdi input 6. interrupts may be lost when writing the timer registers in the asynchronous timer if one of the timer registers which is synchronized to the asynchronous timer2 clock is written in the cycle before a overflow interrupt occurs, the interrupt may be lost. problem fix/workaround always check that the timer2 timer/c ounter register, tcnt2, does not have the value 0xff before writing th e timer2 control register, tccr2, or output compare register, ocr2. 5. high current consumption in powe r down when jtagen is programmed the input buffer on tdo (pf6) is always enabled and the pull-up is always disabled when jtag is programmed. this can leave the output floating. problem fix/workaround add external pull-up to pf6. unprogram the jtagen fuse before shipping out the end product. 4. lcd contrast control the contrast control is not working pr operly when using synchronous clock (chip clock) to obtain an lcd clock, and the chip clock is 125 khz or faster. problem fix/workaround use a low chip clock frequency (32 khz) or apply an external voltage to the lcd- cap pin. 3. some data combinations can result in dim segments on the lcd all segments connected to a common plane might be dimmed (lower contrast) when a certain combination of data is displayed. problem fix/workaround default waveform: if there are any unused segment pins, loading one of these with a 1 nf capacitor and always write ?0? to this segment eliminates the problem. low power waveform: add a 1 nf capacitor to each common pin. 2. lcd current consumption in an interval where v cc is within the range vlcd -0.2v to vlcd + 0.4v, the lcd current consumption is up to three time s higher than expected. this will only be an issue in power-save mode with the lcd running as the lcd current is negligible compared to the overall power consumption in all other modes of operation. problem fix/workaround no known workaround. 1. idcode masks data from tdi input the jtag instruction idcode is not workin g correctly. data to succeeding devices are replaced by all-ones during update-dr.
19 atmega169/v 2514ps?avr?07/06 problem fix / workaround ? if atmega169 is the only device in the scan chain, the problem is not visible. ? select the device id register of the atmega169 by issuing the idcode instruction or by entering the test-logic-reset state of the tap controller to read out the contents of its device id register and possibly data from succeeding devices of the scan chain. issue the bypass instruction to the atmega169 while reading the device id registers of preceding devices of the boundary scan chain. ? if the device ids of all devices in the boundary scan chain must be captured simultaneously, the atmega169 must be the first device in the chain. atmega169 rev b ? interrupts may be lost when writing the timer registers in the asynchronous timer ? internal oscillator runs at 4 mhz ? lcd contrast voltage is not correct ? external oscillator is non-functional ? usart ? adc measures with lower accuracy than specified ? serial downloading ? idcode masks data from tdi input 8. interrupts may be lost when writing the timer registers in the asynchronous timer if one of the timer registers which is synchronized to the asynchronous timer2 clock is written in the cycle before a overflow interrupt occurs, the interrupt may be lost. problem fix/workaround always check that the timer2 timer/c ounter register, tcnt2, does not have the value 0xff before writing th e timer2 control register, tccr2, or output compare register, ocr2. 7. internal oscillator runs at 4 mhz the internal oscillator runs at 4 mhz inst ead of the specified 8 mhz. therefore, all flash/eeprom programming times are twic e as long as specified. this includes chip erase, byte programming, page programming, fuse programming, lock bit programming, eeprom writ e from the cpu, and flash self-programming. for this reason, rev-b samples are shipped with the ckdiv8 fuse unprogrammed. problem fix/workaround if 8 mhz operation is required , apply an external clock (this will be fixed in rev. c). 6. lcd contrast voltage is not correct the lcd contrast voltage between 1.8v and 3.1v is incorrect. when the v cc is between 1.8v and 3.1v, the lcd contrast voltage drops approx. 0.5v. the current consumption in this interval is higher than expected. problem fix/workaround contrast will be wrong, but display will still be readable, can be partly compensated for using the contrast control regi ster (this will be fixed in rev. c). 5. external oscillator is non-functional the external oscillator does not run with the setup de scribed in th e datasheet. problem fix/workaround use other clock source (this will be fixed in rev. c).
20 atmega169/v 2514ps?avr?07/06 alternative problem fix/workaround adding a pull-down on xtal1 will start the oscillator. 4. usart writing txen to zero during transmission causes the transmission to suddenly stop. the datasheet description tells that the transmission should complete before stop- ping the usart when txen is written to zero. problem fix/workaround ensure that the transmission is complete before writing txen to zero (this will be fixed in rev. c). 3. adc measures with lower accuracy than specified the adc does not work as intended. there is a positive offset in the result. problem fix/workaround this will be fixed in rev. c. 2. serial downloading when entering serial programming mode the second byte will not echo back as described in the serial programming algorithm. problem fix/workaround check if the third byte echoes back to ensure that the device is in programming mode (this will be fixed in rev. c). 1. idcode masks data from tdi input the jtag instruction idcode is not workin g correctly. data to succeeding devices are replaced by all-ones during update-dr. problem fix / workaround ? if atmega169 is the only device in the scan chain, the problem is not visible. ? select the device id register of the atmega169 by issuing the idcode instruction or by entering the test-logic-reset state of the tap controller to read out the contents of its device id register and possibly data from succeeding devices of the scan chain. issue the bypass instruction to the atmega169 while reading the device id registers of preceding devices of the boundary scan chain. ? if the device ids of all devices in the boundary scan chain must be captured simultaneously, the atmega169 must be the first device in the chain.
21 atmega169/v 2514ps?avr?07/06 datasheet revision history please note that the referring page numbers in this section are referring to this docu- ment. the referring revision in this section are referring to the document revision. changes from rev. 2514o-03/06 to rev. 2514p-07/06 changes from rev. 2514n-03/06 to rev. 2514o-03/06 changes from rev. 2514m-05/05 to rev. 2514n-03/06 changes from rev. 2514l-03/05 to rev. 2514m-05/05 changes from rev. 2514k-04/04 to rev. 2514l-03/05 1. updated ?fast pwm mode? on page 109. 2. updated features in ?usi ? universal serial interface? on page 179. 3. added ?clock speed considerations.? on page 185. 4. updated ?bit 6 ? acbg: analog co mparator bandgap select? on page 191. 5. updated table 49 on page 90, table 51 on page 90, table 56 on page 117, table 57 on page 118, table 58 on page 119, table 61 on page 135 and table 63 on page 136. 6. updated ?prescaling and conversion timing? on page 196. 7. updated features in ?lcd controller? on page 210. 8. updated ?errata? on page 349. 1. updated number of general purpose i/o pins from 53 to 54. 2. updated ?serial peripheral interface ? spi? on page 143. 1. added not recommended in new designs. 2. removed the notice: this datasheet covers revision a to e of atmega169. revision f and onwards are now covered in atmega169 datasheet, ?doc2597.pdf? found on www.atmel.com/avr. 3. updated table 17 on page 40. 1. this datasheet covers revision a to e of atmega169. revision f and onwards are now covered in atmega169 datasheet, ?doc2597.pdf? found on www.atmel.com/avr. 1. mlf-package alternative changed to ?quad flat no-lead/micro lead frame package qfn/mlf?. 2. updated table 16 on page 38, table 56 on page 117, table 57 on page 118, table 98 on page 222, table 99 on page 222, table 100 on page 223 and table 130 on page 283. 3. added ?pin change interrupt timing? on page 51. 4. updated c code example in ?usart initialization? on page 156. 5. added note to ?power reduction register - prr? on page 34 and ?lcd contrast control register ? lcdccr? on page 222. 6. moved ?no. of words in a page and no. of pages in the flash? and ?no. of words in a page and no. of pages in the eeprom? to ?page size? on page 268. 7. updated ?serial programming algorithm? on page 281. 8. updated ?atmega169 typical characteristics? on page 304.
22 atmega169/v 2514ps?avr?07/06 changes from rev. 2514j-12/03 to rev. 2514k-04/04 changes from rev. 2514i-09/03 to rev. 2514j-12/03 changes from rev. 2514h-05/03 to rev. 2514i-09/03 9. renamed ?using the power reduction register? to ?supply current of i/o modules? on page 309. 10. updated ?register summary? on page 7. 11. updated ?ordering information? on page 14. 12. updated figure 83 on page 193, figure 91 on page 200, and figure 123 on page 276. 1. changed size from 0x60 to 0xff in ?stack pointer? on page 11. 2. updated table 17 on page 40, table 21 on page 44 and table 115 on page 264. 3. updated ?calibrated internal rc oscillator? on page 27. 4. added new ?power reduction register? on page 34. examples found in ?supply current of i/o modules? on page 309. 5. fixed typo in port description for the ?analog to digital converter? on page 192. 6. removed old and added new ?lcd controller? on page 209. 7. updated ?electrical characteristics? on page 297. 8. updated ?atmega169 typical characteristics? on page 304. 9. updated ?ordering information? on page 14. atmega169l replaced by atmega169v and atmega169. 1. updated ?calibrated internal rc oscillator? on page 27 1. removed ?advance information? from the datasheet. 2. removed agnd from figure 2 on page 3 and added ?system clock prescaler? to figure 11 on page 23. 3. updated table 16 on page 38, table 17 on page 40, table 19 on page 42 and table 41 on page 72. 4. renamed and updated ?on-chip debug system? to ?jtag interface and on-chip debug system? on page 36. 5. updated com01:0 to com0a1:0 in ?timer/counter control register a ? tccr0a? on page 89 and com21:0 to com2a1:0 in ?timer/counter control register a? tccr2a? on page 135. 6. updated ?test access port ? tap? on page 225 regarding jtagen. 7. updated description for the jtd bit on page 234. 8. added a note regarding jtagen fuse to table 119 on page 267. 9. updated absolute maximum ratings* and dc characteristics in ?electrical characteristics? on page 297. 10. updated ?errata? on page 17 and added a proposal for solving problems regarding the jtag instruction idcode.
23 atmega169/v 2514ps?avr?07/06 changes from rev. 2514g-04/03 to rev. 2514h-05/03 1. updated typo in figure 148, figure 168, and figure 195. changes from rev. 2514f-04/03 to rev. 2514g-04/03 1. updated ?atmega169 typical characteristics? on page 304. 2. updated typo in ?ordering information? on page 14. 3. updated figure 46 on page 109, table 18 on page 40, and ?version? on page 232. changes from rev. 2514e-02/03 to rev. 2514f-04/03 1. renamed icp to icp1 in whole document. 2. removed note on ?crystal oscillator operating modes? on page 25. 3. xtal1/xtal2 can be used as timer oscill ator pins, described in chapter ?cal- ibrated internal rc oscillator? on page 27. 4. switching between prescaler settings in ?system clock prescaler? on page 29. 5. updated dc and acd characteristics in chapter ?electrical characteristics? on page 297 are updated. removed tbd?s from table 16 on page 38, table 19 on page 42, table 134 on page 300. 6. updated figure 23 on page 56, figure 26 on page 60 and figure 110 on page 237 regarding write pinx register. 7. updated ?alternate functions of port f? on page 72 regarding jtag. 8. replaced timer0 overflow with timer/counter0 compare match in ?universal serial interface ? usi? on page 178. also updated ?start condition detector? on page 184 and ?usi control register ? usicr? on page 186. 9. updated features for ?analog to digi tal converter? on page 192 and table 88 on page 204. 10. added notes on figure 118 on page 258 and table 118 on page 266. changes from rev. 2514d-01/03 to rev. 2514e-02/03 1. updated the section ?features? on page 1 with information regarding atmega169 and atmega169l. 2. removed all references to the pg5 pin in figure 1 on page 2, figure 2 on page 3, ?port g (pg4..pg0)? on page 6, ?alternate functions of port g? on page 74, and ?register description for i/o-ports? on page 76. 3. updated table 118, ?extended fuse byte,? on page 266. 4. added errata for ?datasheet revision hi story? on page 20, including ?signifi- cant data sheet changes?.
24 atmega169/v 2514ps?avr?07/06 5. updated the ?ordering information? on page 14 to include the new speed grade for atmega169l and the new 16 mhz atmega169. changes from rev. 2514c-11/02 to rev. 2514d-01/03 1. added tck frequency limit in ?programming via the jtag interface? on page 284. 2. added chip erase as a first step in ?programming the flash? on page 294 and ?programming the eeprom? on page 295. 3. added the section ?unconnected pins? on page 60. 4. added tips on how to disable the ocd system in ?on-chip debug system? on page 35. 5. corrected interrupt addresses. adc and ana_comp had swapped places. 6. improved the table in ?spi timing characteristics? on page 300 and removed the table in ?spi serial programming characteristics? on page 284. 7. changed ?will be ignored? to ?must be written to zero? for unused z-pointer bits in ?performing a page write? on page 259. 8. corrected ?lcd frame complete? to ?lcd start of frame? in the lcdcra register description. 9. changed out to sts and in to lds in usi code examples, and corrected f sckmax . the usi i/o registers are in the extended i/o space, so in and out cannot be used. lds and sts take one more cycle when executed, so f sckmax had to be changed accordingly. 10. removed toskon and tosck from table 103 on page 238, and g10 and g20 from figure 115 on page 240 and table 105 on page 241, because these sig- nals do not exist in boundary scan. 11. changed from 4 to 16 mips and mhz in the device features list. 12. corrected port a to port f in ?avcc? on page 6 under ?pin descriptions? on page 5. 13. corrected 230.4 mbps to 230.4 kbps in ?examples of baud rate setting? on page 174. 14. corrected placing of falling and risi ng xck edges in table 78, ?ucpol bit settings,? on page 173. 15. removed reference to multipurpose oscillator application note, which does not exist. 16. corrected number of calibrated rc oscillator cycles in table 1 on page 19 from 8,448 to 67,584. 17. various minor timer1 corrections.
25 atmega169/v 2514ps?avr?07/06 18. added information about pwm symmetry for timer0 and timer2. 19. corrected the contents of didr0 and didr1. 20. made all bit names in the lcddr re gisters unique by adding the com num- ber digit in front of the two digits already there, e.g. seg304. 21. changed extended standby to adc noise reduction mode under ?asynchro- nous operation of timer/counter2? on page 139. 22. added note about port b having better driving capabilities than the other ports. as a consequence the table, ?dc characteristics? on page 297 was cor- rected as well. 23. added note under ?filling the temporary buffer (page loading)? on page 259 about writing to the eeprom during an spm page load. 24. removed adhsm completely. 25. updated ?packaging information? on page 15. changes from rev. 2514b-09/02 to rev. 2514c-11/02 1. added ?errata? on page 17. 2. added information for the 64-pad mlf package in ?ordering information? on page 14 and ?packaging information? on page 15. 3. changed temperature range and removed industrial ordering codes in ?packaging information? on page 15. changes from rev. 2514a-08/02 to rev. 2514b-09/02 1. changed the endurance on the flash to 10,000 write/erase cycles.
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